To boost the high frequency gain of a differential signal path, the differential high pass circuit 100 of FIG. 1 can be used. Referring to FIG. 1, two input bipolar junction transistors (BJTs) Qa and Qb, which can alternatively be metal oxide semiconductor (MOS) transistors, have an input signal applied differentially across their inputs. Stated another way, the transistors Qa and Qb (also referred to as input devices) receive a pair of input signals. A high pass network 110 is connected between the reference terminals (i.e., the emitters or sources) of the input devices Qa and Qb, to pass high frequency components and block low frequency components of the input signals. The high pass network also provides a bias current feed. A load_a and a load_b are connected, respectively, between the collectors (or drains) of the input devices Q1 and Qb and a high voltage rail (Vsp). Differential outputs (out_a and out_b) of the circuit 100 are provided at a node between the load_a and the collector (or drain) of the transistor Qa and a node between the load_b and the collector (or drain) of the transistor Qb.
The input devices Qa and Qb and the high pass network 110 provide a high pass transconductor that generates an output voltage across load_a and load_b. Because the high pass network 110 is differentially connected, it contributes to the differential output voltage, without adding to the common mode signal at out_a and out_b.
Parasitic capacitances to a low voltage rail (Vsm, e.g., ground or some other low voltage rail, such as, but not limited to, a negative voltage rail), illustrated by Ca, Cb and Cc (shown in dashed line), cause the common mode gain to increase with increases in frequency. If a single stage 100 were used, this may be acceptable. However, when cascading several such stages, as often required to equalize a cable with high frequency loss, the rising gain at higher frequencies will cause undesirable common mode behavior, including but not limited to common mode oscillation.
One way to attempt to suppress the rising gain at higher frequencies is to place capacitors across (i.e., in parallel with each of) load_a and load_b. However, this would suppress the desired increase in differential gain.
Another solution for suppressing common mode gain at higher frequencies is to build in a common mode loop that detects increases in the common mode voltages at the differential outputs using a sum of two output voltages. A high gain amplifier can be used to compare the sum of these two output voltages to a desired reference voltage. The high gain amplifier can also be used to modulate the bias current source and effectively null out the voltages induced in the parasitic capacitance, and more generally, to provide common mode feedback. However, with this solution, because the bandwidth of the high pass network 110 is very wide, it becomes very difficult to make the feedback loop have a wide enough bandwidth to follow the currents. Additionally, as frequencies increase, the high frequency effects of the injected currents are not cancelled, at which points the capacitive currents are at their most severe, since capacitive impedance drops with increases in frequency.